High voltage buildup occurs at input/output (I/O) pads of an integrated circuit (IC) during an electrostatic discharge (ESD) event. This high voltage buildup may cause damage to gate dielectrics of input stage transistors. For example, if the gate to substrate voltage at the input stage transistor is greater than the breakdown voltage (VBD) of the gate dielectric, than transistor may be rendered defective.
Conventional techniques for protecting gate dielectrics include the use of a clamping circuit to limit the voltage seen across the gate dielectric. However, conventional techniques are not very effective in protecting gate dielectrics for newer technologies. This is because the triggering voltage of the clamping circuit is greater than VBD of the gate dielectrics. For example, by the time the clamping circuit is switched on, the voltage across the gate dielectric is already greater than VBD.
It is desirable to provide gate dielectric protection which adequately prevents the voltage across the gate dielectric to be above VBD.